The present invention relates to contacts for microelectronic devices such as semiconductor chips and the associated circuit panels, connectors and related devices to methods of making and using such contacts, and to components such as sockets and other connectors including such contacts.
Microelectronic circuits require numerous connections between elements. For example, a semiconductor chip may be connected to a small circuit panel or substrate, whereas the substrate may in turn be connected to a larger circuit panel. The chip to substrate or “first level” interconnection requires a large number of individual electrical input and output (“I/O”) as well as power and ground connections. As chips have become progressively more complex, the number of I/O connections per chip has grown so that hundreds of connections or more may be needed for a single chip. To provide a compact assembly, all of these connections must be made within a relatively small area, desirably an area about the area of the chip itself. Thus, the connections must be densely packed, preferably in an array of contacts on a regular grid, commonly referred to as a “Bump Grid Array” or “BGA”. The preferred center-to-center distance between contacts or “contact pitch” for chip mountings is on the order of 1.5 mm or less, and in some cases as small as 0.5 mm. These contact pitches are expected to decrease further. Likewise, chip mounting substrates and other circuit panels used in microelectronics have become progressively more miniaturized, with progressively greater numbers of electrical conductors per unit area. Connectors for these miniaturized panel structures desirably also have very small contact pitch. Connections of chip mounting substrates to other elements are referred to as “second-level” inter connections.
In some cases, the connections may include permanent metallurgical bonding of the mating contacts to one another, as by soldering, brazing, thermocompression or thermosonic bonding, welding and the like. For example, electrical contacts on a semiconductor chip may be bonded to the mating contact pads of a substrate by solder bumps. Alternatively, the connection may be made so that the mechanical interengagement of the mating elements provides electrical continuity. Such a connection usually is separable, so that the connected elements can be removed. For example, contacts on a chip may be temporarily engaged with mating contacts of a test fixture under mechanical load.
Microelectronic connections must meet numerous, often conflicting requirements. As mentioned above, the size of the device poses a major concern. Further, such connections often are subject to thermal cycling strains as temperatures within the assembly change. The electrical power dissipated within a chip or other microelectronic element tends to heat the elements so that the temperatures of the mating elements rise and fall each time the device is turned on and off. As the temperatures change, the various connected elements expand and contract by different amounts, tending to move the contacts on one element relative to the mating contacts on the other element. Changes in the temperature of the surrounding environment can cause similar effects.
The connections must also accommodate manufacturing tolerances in the contacts themselves and in the connected elements. Such tolerances may cause varying degrees of misalignment. Additionally, contamination on the surfaces of the mating contact parts can interfere with the connection. This can occur in metallurgically bonded connections and, particularly, in mechanically interengaged connections. Therefore, the contact system should be arranged to counteract the effects of such contaminants. All of these requirements, taken together, present a formidable engineering challenge.
Various approaches have been adopted towards meeting these challenges. For example, Patraw, U.S. Pat. No. 4,716,049; U.S. Pat. No. 4,902,606 and U.S. Pat. No. 4,924,353 all disclose flexible, outstanding projections on a substrate, each such projection being generally dome-shaped. The chip itself is provided with a so-called “mesa” member having multiple conductive pads coupled to the actual contacts of the chip. A spring biases the chip and hence the pads on the mesa member against the dome-shaped members. Minemura et al, U.S. Pat. No. 4,950,173 discloses a relatively coarse-pitched connector in which pin-shaped contacts, thread into holes in insulating support. Contact tabs formed from a shape memory alloy are then brought into engagement with the pin by changing the temperature, causing the tabs to change shape and hence engage the pin. This provides a so-called “zero insertion force” system in which the pin is not engaged or wiped by the tabs. Hotine et al, U.S. Pat. No. 3,275,736 also discloses a relatively coarse, second-level interconnect structure. In this structure, all contact including a ring with a plurality of fingers extending inwardly from the ring is engaged on a pin-like lead extending from a microelectronic component. Each of the fingers has a point at its tip, and these points scrape the leads as the parts are engaged. Once the parts are engaged, the fingers may be metallurgically bonded to the leads as by welding. Shreve et al, U.S. Pat. No. 5,046,953 describes a tape automating bonding or “TAB” arrangement using a dielectric tape with conductive leads thereon in which the leads themselves are dimpled or in which sets of spherical particles are interposed between the leads and the mating contacts so as to provide an indenting and scrubbing action when the leads of the tape are pressed against the contacts. Grabbe, U.S. Pat. No. 5,173,055 discloses a “area array connector” including plate-like springs with upwardly projecting fingers to the main gauge plate-like contacts on the mating part. U.S. Pat. No. 5,152,695 discloses similar arrangements, in which the fingers are provided with apparently rounded or spherical raised bumps formed by adding a raised area of gold using a wire bonding machine and then “mechanically profiling” the raised area or by welding a gold wire onto the contact finger and coining the wire into the final shape. Grabbe et al, U.S. Pat. No. 5,131,852 discloses a tape-based connection system in which contacts on a flexible tape are supported by spring fingers and thus pressed against contact pads on semiconductor chip. Here again, the contacts are provided with rounded raised sections formed by electroforming, wire bonding or the like.
Ikeya, U.S. Pat. No. 4,846,704 discloses a test socket for testing large, second level interconnections, the test socket having numerous spring fingers which engage the exposed leads connected to the chip. Each of these spring fingers has sharp edges for making contact with the exposed lead. Still other connectors are disclosed in the text Multi-chip Module Technologies and Alternatives; The Basics, Donn et al, EDS, Van Nostrand Rhinehold Company 1993, Chapter 10, (pp. 487-524) entitled MCM To Printed Wiring Board (Second Level) Connection Technology Options, by Alan D. Knight.
Evans et al, U.S. Pat. No. 3,818,415 discloses a large-scale electrical connector having a contact surface with adhering fine particles of a grit, these particles being covered by tough, metal coating. These particles are said to scrape away adhering insulation on a mating conductor. Hill et al, Mechanical Interconnection System For Solder Bump Dice, 1994 ITAP and Flip Chip Proceedings (pp. 82-86) disclose a test connector for engaging solder bumps on microelectronic chips. The connector includes a flat surface with a set of pads in an array corresponding to the array of solder bumps on the pads. Each pad on the fixture has a so-called “dendritic” or “random pattern” of small palladium needles, typically about 200-500 needles per square millimeter. These needles or dendrites are forced against the solder bumps during use, so that the dendrites penetrate contaminant films on the solder bumps and make electrical contact.
Caine et al, U.S. Pat. No. 5,006,917 describes a tape automated bonding system in which a dielectric tape is provided with multiple leads, all having exposed inner tips. These tips are provided with non-dendritic, rough surfaces having ridges spaced apart from one another at a peak-to-peak distance of approximately 1 micron. These lead tips are then bonded to pads on a semiconductor chip by thermocompression bonding.
Burns et al, U.S. Pat. No. 5,207,585 describes a “interface pellicle” including a flexible, dielectric membrane and a large number of electrodes extending through the dielectric membrane. Each electrode has a dome-like upper surface disposed on the top surface of the membrane and a roughened bottom surface disposed on the bottom side of the membrane. The pellicle can be used by placing the membrane between a mounting substrate having contact pads and a chip or other component having solder balls so that the textured bottom surface of the electrodes face the solder balls whereas the dome-like top surfaces face the contact pads of the substrate. The substrate and the component are then forced together so that each electrode is squeezed between a contact pad and a solder pad. The rough bottom surfaces indent the surfaces of the solder balls.
Despite these efforts in the art, there has still been a need for further improvement.